This paper describes a motion estimation (ME) processor core for realtime, MP@HL video encoding. It is being fabricated with 0.13um CMOS technology and contains approximately 7 M-transistors on 4.50"x 3.35" area. The estimated power consumption is less than lOOmW at SlMHz@l.OV. It features a Gradient Descent Search (GDS) algorithm that drastically reduces the required computation power to 7GOPS, an optimized SIMD datapath architecture that decreases the clock frequency and the operating voltage, and a low power 3port data cache SRAM with a writs disturb-free cell m y arrangement. The core can be applicable to a portable HDTV codec system. IntroductionA portable HDTV system such as a MPEG camera becomes more popular if people sends and receives a video mail using the broadband network. To realize a high quality and low power MPEG codec in the system, a highly efficient ME processor is essential, because the conventional ME technique requires more than 90% performance of the codec. Figure1 shows the power consumption trend of a ME processor. The power consumption in the 0.13um processor developed with the conventional technology is more than 1200mW even for 1/4 sub-sampling technique. This is too large for portable products.Several MPEG codec LSIs have been reported [I-31. These LSIs perform MP@ML video encoding. These cannot perform ME for HDTV resolution video with a single chip confieuration. 0.25 0.18 0.13 0 10 007 0.05 0 035 Silicon Technology [um]Fig. 1 Power Consumption Trend of ME Processor Figure2 shows the plot image of the newly developed ME processor. The features are as follows: 0 The GDS algorithm [4] is introduced for motion estimation. The GDS algorithm realizes ME for HDTV resolution video only with 7GOPS computation power, though the conventional full search (FS) algorithm requires about 1000GOPS.A SIMD datapath architecture optimized for the GDS algorithm is designed. The SIMD datapath contains 32 processing elements (PE). It can calculate mean square error (MSE) in 8 cycles per 1 macro block (MB). Its performance is lOGOPS at SlMHz@l.OV. It operates at low frequency and low voltage, so that its power consumption is quite low.The 32Kb 3-port SRAM macro that has a writsdisturbfree cell arrangement with a symmtrical memory cell layout is newly introduced. The estimated power consumption of this SRAM macro is 1.32mW at 1.OV and 81MHz. 0 0The above design techniques result in the realization of an ultra low power motion estimator. The characteristics of the motion estimator are as follows: 0 It can perfom ME for HDTV resolution video in realtime, assuming 1920 x 1080 pixels resolution, 30fps of frame rate, and*128 x 364 of search range. The estimated power consumption is less than lOOmW at the condition of 1.OV apply voltage and 81MHz clock frequency. 0

This paper describes a kind of vision chip, which is an integration of an image processing circuit with photo receptors, that has a function of extracting objects' positions in focal plane. The objects' positions are output as their coordinates, which are useful for further detailed image recognition processing. The extraction processing has two steps; first, the flags indicating the objects' center positions are generated by analog parallel processing circuit implemented by resistive network and comparators, and next, the coordinates of such flags are generated by-and-priority encoders and a novel successive masking circuit. The designed circuit is capable of centroid detection for 23 23 pixels within 50 s, and the processing time is expected not to increase so much even if the number of pixels increases, which will represent an improvement over the conventional processor-based image processing system. We also proposed and evaluated another implementation of a centroid detector using pulse-width adder.

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SUMMARYSince the coordinates of multiple points cannot be encoded simultaneously due to the encoder characteristics when encoding the positions of multiple points on a plane as the coordinates, each point must be successively searched for, and each coordinate must be encoded in order. Highly efficient algorithms to search for points on a plane, such as the binary search, are known. These algorithms can be easily implemented in software in general, but are difficult to implement in hardware. In this paper, we propose an algorithm that rapidly searches for the points on a plane and its circuit architecture in order to encode multiple points. We used this proposed circuit in the last stage of a circuit that detects the centroids of objects on a pixel plane and searched for the detected centroids by a circuit simulation in H-SPICE. From the result, we verified the completion of the search of a 15 × 15-pixel plane in several microseconds. Since the processing time of this algorithm depends, in theory, on the number of points to be searched for and not on the number of pixels on the pixel plane, even as the number of pixels on the pixel plane to be searched increases, the processing time does not increase dramatically. Therefore, this algorithm is also effective as the resolution improves.