One of the established unstable power swing (out-of-step) detection algorithms in micro grid/smart grid power systems uses a trajectory of apparent impedance in the R-X plane. However, this algorithm is not suitable for fast out-of-step conditions and it is hard to detect out-of-step conditions exactly. Another algorithm for out-of-step detection is using phasor measurement units (PMUs). However, PMUs need extra equipment. This paper presents the out-of-step detection algorithm using the trajectory of complex power. The trajectory of complex power and generator mechanical power is used to identify out-of-step conditions. A second order low pass digital filter is used to extract the generator mechanical power from the complex power. Variations of complex power are used to identify equilibrium points between stable and unstable conditions. The proposed out-of-step algorithm is based on the modification of assessment of a transient stability using equal area criterion (EAC). The proposed out-of-step algorithm is verified and tested by using alternative transient program/electromagnetic transient program (ATP/EMTP) MODELS.

As the memory footprint of emerging applications keeps increasing, the address translation becomes a critical performance bottleneck due to frequent misses on TLB. In addition, the TLB miss penalty becomes more critical in modern computer systems because the levels of the hierarchical page table (a.k.a. radix page table) are increasing to extend address space. In order to reduce the TLB misses, modern highperformance processors employ a multi-level TLB structure that uses a large last-level TLB. Employing a large last-level TLB might reduce the TLB misses. However, its capacity is still limited, and it can incur chip area overheads. In this paper, we propose a PSE Pinning mechanism that provides a large PSE (Page Structure Entry) store by dedicating some space of the last-level cache for only storing the page structure entries. PSE Pinning is based on three key observations. First, memory-intensive applications suffer from frequent misses on the last-level cache. Thus, most space of the last-level cache is not well utilized. Second, most PSEs are fetched from the main memory during the page table walk process, meaning the cache lines for the PSEs are frequently evicted from the on-chip caches. Lastly, a small number of PSEs are frequently accessed while others are not. By exploiting these three observations, PSE Pinning pins the frequently accessed page structure entries to the last-level caches so that they can reside on the cache. Experimental results show that PSE Pinning improves the performance of memory-intensive workloads suffering from frequent L2 TLB misses by 7.8% on average.

Power quality and stability have become the most important issues in power system operations, Micro Grids, and Smart Grids. Sensitive equipment can be seriously damaged when exposed to unstable power swing conditions. An unstable system may cause serious damage to Micro Grid System elements such as generators, transformers, transmission lines, and so forth. Therefore, out-of-step detection is essential for the safe operation of a Micro Grid system. In general, Equal Area Criterion (EAC) is a method for evaluating the stability of Smart Grid systems. However, EAC can be performed only if it is possible to analyze the active power and generator angle. This paper presents an analysis of the trajectory of complex power using a mathematical model. The variation of complex power is analyzed using a mathematical method, and then the relationship between complex power and EAC is presented, and a simulation performed. Later, in part II, a novel out-of-step detection algorithm based on part I will be presented and tested.

No abstract

No abstract