Electromagnetic interference (EMI) in electronic products such as home theater systems or DVD players is a real issue that must be dealt with. Among all the techniques used to reduce the radiated power, a popular one is to modulate the system clock of the computing devices such that the radiated power level in a given bandwidth is lower. The standard bandwidth for this type of measurement is 120kHz. This technique is called spread spectrum clock generation (SSCG).The commonly used technique to produce SSCG is an "all analog" one where modulation is applied or inserted into a phased lock loop (PLL). The frequency can be modulated by imposing a signal on the voltage control node of a VCO [1] or by using a "fractional N" technique that changes the divider ratio [2]. The technique presented in this paper does not use any PLL or "analog" circuits. The circuit (0.06mm 2 ) is fabricated in a 0.15µm CMOS process and consumes 7.1mW for the application of 27MHz.The entire circuit is based on a digital delay line (DDLi) with a small logical circuit to control it. The DDLi is used to modulate an input clock. The size of the DDLi is limited to one period of the input clock and several techniques are developed to allow adequate frequency modulation and frequency deviation. The principle logic circuits used include the "wrap around circuit" (the removal of one period delay in the delay line), the circuit that cancels one intrinsic delay inside the DDLi and the circuit that performs calibration.The DDLi is made from 384 (24×16) inverter buffers placed on a matrix multiplexer. The first 16 taps are duplicated and each of their outputs is connected to a bank of D-type flip-flop as shown in Fig. 14.2.1. This arrangement is used to monitor the arrival of the rising edge in the DDLi. In the design of the duplicated row, it is critical to compensate the delay of the multiplexer switch with the same delay in front of the duplicated row. The remaining uncompensated delay is the delay from the output of the clock to the input clock of the D-type flip-flop and this delay is cancelled out in the digital section. Figure 14.2.2 shows the basic delay cell and Fig. 14.2.3 shows the actual delay of approximately 200ps. The delay cell is made with two NMOS devices driven with a differential signal from the previous cell. The NMOS load is a pair of cross-coupled PMOS devices inside the box labeled "pload" (see Fig. 14.2.2). It is basically a differential input / differential output inverter. Each delay cell drives the following identical cell. The wire X and Z in that cell are the grid of the matrix multiplexer. The delay cell is connected to the lower gates all the time so that the delay does not change when the row is selected. So each delay cell sees the same load.The logical circuit designed to control the DDLi is shown in Fig. 14.2.4. For a desired frequency modulation and frequency deviation, the user sets registers in the calibration module. This calibration is done by searching for the number of taps per period and hence takes into accou...