Digital signal processing typically requires large number of mathematical operations to be performed repeatedly on the samples of data with less delay and power consumption. Multiplication is the fundamental arithmetic operation and determines the overall execution time of the processor. In this paper two high speed 32-bit Vedic multipliers are designed based on Urdhva-Triyakhbhyam sutra. Addition of partial products of proposed multipliers is done using Kogge stone adder and ripple carry adder respectively. Proposed multiplier-1 and proposed multiplier-2 were compared with the one with the highest speed and a reduction of 77% and 65.37% is achieved respectively. The coding is done using Verilog HDL and synthesized using cadence tool.

Sub-threshold Adiabatic Logic (SAL) is a power saving technique used in VLSI circuit design for applications where power saving is of primary importance. An 8-Bit ALU is designed and implemented based on Sub-Threshold Adiabatic Logic (SAL) using Cadence 45nm technology node. Initially basic blocks decoder, adder and multiplexer are designed and tested for their functionality. Designed basic blocks are integrated to design 8-Bit ALU. Designed ALU is simulated for different inputs to check its functionality. Propagation delay, average power delivered by source, and Power Delay Product (PDP) are computed to compare with CMOS implementation of ALU. A 40db improvement in relative power consumed is observed in SAL compared to CMOS logic. Physical design of the ALU is built to compute chip area of the designed ALU and the total chip area observed is 32,190 um 2 with area utilization of 89%..