Abstract-We report on the development of a submicron InP DHBT technology, optimized for the fabrication of ≥50-GHzclock mixed-signal ICs. In-depth study of device geometry and structure has allowed to get the needed performances and yield. Special attention has been paid to critical thermal behavior. Various size submicron devices have been modeled using UCSD-HBT equations. These large signal models have allowed the design of 50-GHz clocked 50G Decision and 100G Selector circuits. The high quality of the measured characteristics demonstrates the suitability of this technology for the various applications of interest, like 100 Gbit/s transmission.

A 3-bit power-DAC was designed and fabricated in 0.7 mm InP doubleheterojunction bipolar transistor (DHBT) technology. An 8-level differential output signal with 3.6 V pp amplitude was measured at symbol rates in the range of 40 GBd. The circuit combines DAC and driver functions allowing to directly drive a modulator without need for a linear amplifier. This compact IC solution is suitable for transmitters with advanced modulation formats like 64-QAM operating at high symbol rate.Introduction: High capacity optical transmission systems with optimised spectral efficiency are presently being intensively investigated [1]. Modulation formats offering spectral efficiency superior to on/off keying and in particular multilevel coded transmission such as M-ary quadrature amplitude modulation (M-QAM) and operating at high symbol-rate are of particular interest.Different solutions are presently investigated to realise QAM transmitters. The optical multimodulator transmitters combine binary signals in the optical domain. An alternative option is to apply multilevel electrical signals to the much simpler I/Q modulator.The most popular architecture for generation of a multilevel electrical signal is composed of a high-speed electrical digital-to-analogue converter (DAC) followed by a broadband linear amplifier. DACs with important numbers of bits are used which is leading to complex architecture and high power consumption.A 6-bit DAC fabricated in SiGe HBT [2] presents 1.6 V differential amplitude and operates up to 32 GBd. A 6-bit DAC realised in InP HBT technology with very low power consumption is reported in [3]. However, the electrical signal for 28 GBd 16-QAM transmission obtained with this DAC has a differential amplitude limited to 300 mV. A multiformat transmitter for 64-QAM operating at 28 GBd based on the DAC reported in [2] has been presented in [4]. In all the above cited transmitters, the DAC output signal needs to be amplified to correctly drive the modulator. For high frequency operation, amplifiers with sufficient linearity and dynamic are an important design challenge. Additionally, in such system architecture, the intermediate level distortions and noise are amplified and impair transmission quality.In this Letter, we propose an architecture based on a power-DAC concept in which two operations, (i) combination of three input data streams to create multilevel signals and (ii) amplification, necessary for a modulator driver, are realised simultaneously with all circuit elements operating in digital instead of a mixed digital-analogue way. A 3-bit power-DAC has been realised, but this concept can be applied to an arbitrary number of bits.