Reduction of electrical parameter variation is essential to achieve high yield and reliability in semiconductor devices. However, variation depends on a large number of process factors, which are often interdependent. In this work, well-calibrated Technology Computer-Aided-Design process and device simulations were performed in a designed experiment to develop an efficient, surrogate response surface model (RSM) of the device parameters as a function of key process factors. Monte Carlo simulations were performed with the RSM to estimate variation and design systems to reduce variation. The approach, illustrated here specifically for peripheral n-type field-effect transistors in a dynamic random-access-memory process flow, is general, easy-to-implement, and a cost-effective way to systematically identify, model, and analyze process variation.