The interaction of Cu with Si separated by thin (50 nm) layers of tantalum, Ta2N, and a nitrogen alloy of Ta has been investigated to determine the factors that affect the success of these materials as diffusion barriers to copper. Intermixing in these films was followed as a function of annealing temperature by in situ resistance measurements, Rutherford backscattering spectra, scanning electron microscopy, and cross-section transmission electron microscopy. Ta prevents Cu-silicon interaction up to 550 °C for 30 min in flowing purified He. At higher temperatures, copper penetration results in the formation of η″-Cu3Si precipitates at the Ta-Si interface. Local defect sites appear on the surface of the sample in the early stages of this reaction. The Ta subsequently reacts with the substrate at 650 °C to form a planar hexagonal-TaSi2 layer. Ta silicide formation, which does not occur until 700 °C in a Ta-Si binary reaction couple, is accelerated by the presence of Cu. Nitrogen-alloyed Ta is a very similar diffusion barrier to Ta. It was found that Ta2N is a more effective barrier to copper penetration, preventing Cu reaction with the substrate for temperatures up to at least 650 °C for 30 min. In this case, local Cu-Si reaction occurs along with the formation of a uniform Ta5Si3 layer at the Ta2N-Si interface.

We have investigated the effectiveness and failure mechanism of thin tantalum layers as diffusion barriers to copper. 50 nm tantalum films were sputtered onto unpatterned single-crystal 〈100〉 Si wafers and overlaid with 100 nm Cu. Material reactions in these films were followed as a function of annealing temperature by in situ resistance measurements, and characterized by Rutherford backscattering spectroscopy and cross-section transmission electron microscopy. While pure Cu on Si reacts at 200 °C, the Ta film prevents Cu silicon interaction up to 600 °C. At higher temperatures, reaction of the Si substrate with Ta forms a planar layer of hexagonal TaSi2. Cu rapidly penetrates to the Si substrate, forming η″-Cu3Si precipitates at the Ta-Si2-Si interface.

We report a procedure that uses microcontact printing and wet chemical etching to fabricate patterned films of indium tin oxide (ITO) and indium zinc oxide (IZO). The procedure consists of three steps: (1) inking a patterned elastomeric stamp with an alkanephosphonic acid; (2) microcontact printing to form a patterned multilayer film of alkanephosphonic acid on the surface of an ITO or IZO film; (3) etching the unprotected regions of the ITO or IZO film using 0.05 M oxalic acid as the etchant. We demonstrate this procedure by fabricating patterned ITO and IZO films with areas as large as 15 cm 2 and minimum feature sizes of ∼2 µm. The key step in this procedure is applying the alkanephosphonic acid ink to the surface of the stamp. We present two different inking methods to illustrate the impact of stamp inking on the quality of printed and etched ITO and IZO films.

The thin-film transistor (TFT) array of liquid-crystal displays (LCDs) comprises a number of metallic, semiconducting, and insulating layers, which need to be deposited and patterned accurately with very high yields on a (large) glass substrate. We are exploring how to fabricate the gate metal lines of the TFT array in an entirely new and potentially cost-effective waysby depositing the metal layer of the TFT array using electroless deposition (ELD) and by patterning the gates using microcontact printing (µCP). To achieve this goal, we separately explore first the plating conditions to deposit a gate metal on 15 in. glass substrates, and second the printing process to finally combine them later in the work. Here, we review in depth the metallization of the glass by ELD of NiB as gate material, and we demonstrate the patterning of the gate layer using a conventional photoengraving process (PEP, i.e., photolithography and wet etching). We selected NiB because this material can fulfill the conductivity requirements for making an SXGA (1280 pixels × 1020 pixels) display having a 157 pixel per inch resolution. Because ELD requires the presence of a catalyst on the substrate, we derivatized the glass by grafting 3-(2-aminoethylamino)propyltrimethoxysilane (EDA-Si) from an aqueous solution, which serves as linker between the glass and colloidal Pd/Sn particles. We identify the optimum conditions for the derivatization of the glass and to activate it with colloidal Pd/Sn in a uniform manner so as to electroless deposit high-quality NiB layers. We plated uniform NiB films of 120 nm thickness on both faces of 15 in. glass substrates, and we removed the NiB from one face of the substrate using HNO3 dissolved in water. The remaining NiB layer was patterned using a mask of photoresist and an etch bath comprising an aqueous solution of 3-nitrobenzenesulfonic acid (NBSA) and ethylenediamine (EDA) at pH ∼ 9. This etch system minimizes the galvanic coupling between the Pd/Sn particles and the NiB, and it enabled patterning the gates with an accuracy better than 1 µm. Annealing the NiB layer at 400 °C reduces its specific resistivity from 25 to 13 µΩ cm, and the roughness and adhesion of the layer to the glass enable the plasma deposition of silicon nitride (SiN x) and amorphous silicon (a-Si) layers over the patterned array of gates. Building an array of TFTs for a SXGA display using the NiB as the gate layer yielded transistors with transfer and output characteristics similar to those fabricated using a conventional gate material. The work presented here may spur the introduction of novel surface chemistry processes into flat-panel-display factories.

We demonstrate remarkably rapid oxidation of (100) silicon at room temperature catalyzed by the presence of Cu3Si. Thermal oxidation of Si is normally carried out at temperatures above 700 °C. Oxidation of many metal silicides occurs more rapidly than that of Si, but under controlled conditions results in a surface layer of SiO2. In contrast, the oxidation process described here produces a thick layer of SiO2 underneath the copper-rich surface layer. The SiO2 layer grows spontaneously to over 1 μm in thickness in several weeks in air at room temperature. Analysis by Rutherford backscattering, Auger electron spectroscopy, cross-sectional transmission electron microscopy, and scanning electron microscopy reveals the presence of Cu3Si at the buried SiO2/Si interface, epitaxially related to the underlying Si substrate. Catalytic action by this silicide phase appears responsible for the unusual oxidation process.