A systematic study of the growth of high-quality films of GaAs on Si substrates has been performed for applications in devices, particularly in optoelectronic devices for cointegration in optical interconnects. The effort for optimized active layers was approached through the separate optimization of substrate preparation, growth time parameters, and postgrowth treatment. In particular, the study of growth involved the investigation of the effect of silicon substrate orientation, post-growth treatment, as well as multilayer and, especially, silicon buffer layers. For quantification of film quality, a number of characterization methods were used both in situ: reflected high-energy electron diffraction (RHEED); and ex situ: optical, electrical [current versus voltage (I-V), capacitance versus voltage (C-V), deep-level transient spectroscopy (DLTS), Hall], transmission electron microscopy (TEM), scanning electron microscopy (SEM), electron channeling patterns, x-ray double-crystal diffractometry (DDX). Schottky diodes, p-n heterojunctions, and metal-semiconductor-metal photoconductors/photodetectors (MSM PC/PDs), field-effect transistors, and high electron mobility transistors were fabricated on these films. The most crucial parameter for device operation and film uniformity is the complete absence of antiphase boundaries which increase leakage, degrade mobilities, and seem to result in interface two-dimensional electron gas in substrates misoriented toward 〈110〉.
Absolutely smooth GaAs morphology is obtained using a molecular-beam epitaxy grown Si buffer layer and controlling the orientation of the GaAs film so that the [110] direction is parallel to the 〈110〉 misorientation direction of the vicinal (001) substrates. This can be ensured by an As4 prelayer grown at 350 °C. A double 2×1 domain Si surface seems to be preferable, as it allows the choice of such a GaAs orientation. GaAs growth is then 2D from the very early stages of growth, following the homogeneous nucleation of 3D GaAs islands, resulting in the complete elimination of planar faults. A perfectly regular displacement-type moiré pattern in the GaAs/Si interface is then observed. GaAs buffers on Si with an MBE Si buffer exhibit high resistivity, probably due to growth on contamination-free surfaces. The lowest ever reported 1 μm DDX full width at half-maximum of 255 arcsec was observed for such a GaAs/Si/Si layer. Nevertheless, accurate TEM dislocation counts indicate a dislocation density in the low 108 cm−2 range. In addition, a saturation in DDX FWHM values appears for an epilayer thickness of about 2 μm. This may be related to values being limited by wafer bowing or it may indeed reflect a limit in film quality. Post-growth rapid thermal annealing results in redistribution of dislocations in a nonuniform way with most congregating in small areas of high dislocation density, leaving large areas with low dislocation density.
It is concluded that by either increasing the GaAs epilayer thickness or the sample temperature one produces a residual compressive stress that forces the threading dislocations to slip, thus reducing their density by reactions that become moreprobable with proximity. The residual dislocation density of about 108 cm−2 is attributed partly to threading dislocation generation during the early stages of epitaxy and only partly to generation from tensile thermal stress during cooling. Schottky diodes on GaAs/Si break down at the same or similar voltages as on homoepitaxial material. MSM PC/PDs have comparable dark dc leakage currents, somewhat lower dc photoresponse, and comparable rise and fall times, and metal-semiconductor field-effect transistors (1.5 μm gate length) fabricated on GaAs/Si/Si show a maximum extrinsic transconductance of 230 mS/mm, actually somewhat higher than for homoepitaxial devices. Thus, device results allow us to claim that we have achieved a technology that leads to heteroepitaxial GaAs/Si films which compare in performance to homoepitaxial GaAs/GaAs within about 10% for applications in most devices. The use of an MBE Si buffer layer, in addition to improving the quality of the GaAs layer, results in a reduction of a processing temperature by at least 100 °C. This reduction, along with the elimination of the step-doubling processing step, makes GaAs film growth compatible to unmetallized fully processed complementary metal-oxide-semiconductor (CMOS) Si wafers.
