The SwissFEL X-ray Free Electron Laser (XFEL) facility started construction at the Paul Scherrer Institute (Villigen, Switzerland) in 2013 and will be ready to accept its first users in 2018 on the Aramis hard X-ray branch. In the following sections we will summarize the various aspects of the project, including the design of the soft and hard X-ray branches of the accelerator, the results of SwissFEL performance simulations, details of the photon beamlines and experimental stations, and our first commissioning results.

The SwissFEL Injector Test Facility operated at the Paul Scherrer Institute between 2010 and 2014, serving as a pilot plant and testbed for the development and realization of SwissFEL, the X-ray Free-Electron Laser facility under construction at the same institute. The test facility consisted of a laser-driven rf electron gun followed by an S-band booster linac, a magnetic bunch compression chicane and a diagnostic section including a transverse deflecting rf cavity. It delivered electron bunches of up to 200 pC charge and up to 250 MeV beam energy at a repetition rate of 10 Hz. The measurements performed at the test facility not only demonstrated the beam parameters required to drive the first stage of an FEL facility, but also led to significant advances in instrumentation technologies, beam characterization methods and the generation, transport and compression of ultra-low-emittance beams. We give a comprehensive overview of the commissioning experience of the principal subsystems and the beam physics measurements performed during the operation of the test facility, including the results of the test of an in-vacuum undulator prototype generating radiation in the vacuum ultraviolet and optical range.

The design, construction and performance of the H1 silicon vertex detector is described. It consists of two cylindrical layers of double sided, double metal silicon sensors read out by a custom designed analog pipeline chip. The analog signals are transmitted by optical fibers to a custom designed ADC board and are reduced on PowerPC processors. Details of the design and construction are given and performance figures from the first data taking periods are presented.

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