This paper presents a two-dimensional hot-carrier simulator which calculates the spatial distribution of hot electron and hot hole emission currents along the Si-SiO2 interface of MOS transistor. The simulation are compared to experimental hot-carrier degradations for a n-channel transistor and different stress bias conditions. It is shown that hole injection effects are only dominant at low gate voltages and that the usual correlation between degradation and substrate current may be attributed only to hot electrons