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The scalabilty of the titanium self-aligned silicide (Salicide) process is one of the main issues for sub-quarter micron technologies. The major difficulty is to achieve a low sheet resistance for very narrow polysilicon lines and highly doped S/D regions, without degrading the transistor performance. A preamorphization implant (PAl) performed before the titanium deposition, can achieve a low Ti silicide sheet resistance (<10 Ohms/sq) down to 0.1 Vim gate lengths [1]. Nevertheless, it has been recently reported that PAI should not be sufficient to achieve low silicide sheet resistance for narrower gate widths (< 0.1 µm) [2]. In this work, an extension of the PAI process down to 0.065µm poly-Si lines width, by only using an arsenic implant is presented, achieving a very low sheet resistance value (∼5 Ohms/sq). This result has been obtained by optimizing both the arsenic implant conditions and the silicon surface cleaning. Moreover, a large statistical analysis of the arsenic PAI process impact on 0.25µm device performances has been done, showing that a defectivity of the NMOS Ioff leakage current can appear if preamorphization implant conditions are not optimized.

A new failure mechanism was studied on high density and high performances 0.25µm SRAM memories. A local anomalous polysilicon grain growth, promoted by a Phosphorus gate predoped implantation, induced a modification of dopant diffusion into N-doped transistor gate. This local variation of small transistor threshold voltage, was responsible for a severe yield loss in large SRAM memory array. This phenomenon was both related to gate material properties and gate predoped implantation conditions. This paper presents a complete characterization of this new failure mechanism, based on physical and electrical measurements. Finally, main results of process experiments, performed to solve the problem, are discussed.