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Transconductance efficiency (gm/ID) is an essential design synthesis tool for low-power analog and RF applications. In this paper, the invariance of gm/ID versus normalized drain current curve is analyzed in an asymmetric double gate fully depleted MOSFET. The paper studies the breakdown of this invariance versus back gate voltage, transistor length, temperature, drain to source voltage and process variations. The unforeseeable invariance is emphasized by measurements of a commercial 28 nm UTBB FDSOI CMOS technology, thus supporting the gm/ID based design methodologies usage in double gate FDSOI transistors sizing.

In this paper, we present the first complete compact model dedicated to Ultra-Thin Body and Box and Independent Double Gate MOSFETs based on an explicit formulation of front and back surface potentials that is valid and extremely accurate in all operation regimes. The model provides physics-based consistent description of DC and AC device characteristics; it has been extensively validated against TCAD and hardware data, and fulfills standard requirements from quality assurance and convergence tests for circuit design.