Direct delta-sigma receiver architecture is introduced for wireless communication systems, such as LTE or WiMax. Architecture is based on direct downconversion, delta-sigma feedback that is up-converted to RF, and N-path filtering technique. Hence, the core receiver functions including channel selection filtering are embedded to a RF ADC with excellent linearity performance. This is achieved by transforming narrow-band filtering partially to RF injecting feedback into the input of the second amplifier stage, hence relieving requirements of the most critical subsequent stages. A 900-MHz direct delta-sigma receiver prototype occupies an active area of 1 2 mm 2 in 65-nm CMOS. The receiver for low-band cellular operations achieves NF of 2.3 and 6.2 dB in conventional and delta-sigma modes, respectively, and out-of-band IIP3 up to +4 dBm when the delta-sigma loop is active. The chip consumes 80 mW from a 1.2-V supply.

No abstract

Wireless communications is moving towards higher data rates but also requiring dynamic scalability of signal bandwidths in LTE to allow more optimization opportunities at the network level. At the same time consumer devices are providing multiple active radio connections simultaneously, resulting in an extremely hostile interference environment due to intra-device coupling. Especially the trade-off between off-chip, passive out-of-band filtering and linearity remains a major challenge in highly optimized FDD systems like WCDMA [1] or LTE. Local RF loops have been proposed to remove the highest blockers [2] but still most of the commercial receivers e.g.[3] are adopting conventional direct-conversion or low-IF architectures. Various sampling techniques [4] including the bandpass ΔΣ approach [5] have been presented as solutions for a software-defined radio (SDR). However, they cannot address the RF linearity issue, and especially ΔΣ converters suffer from limited dynamic range and in many cases also from excessive power consumption. In this paper, a direct-conversion ΔΣ receiver architecture is proposed that can improve out-of-band linearity with an RF feedback loop as well as providing 56dB of SNDR for the 9MHz LTE signal. The prototype is not specifically designed to meet the LTE specification but it provides a flexible architecture for receivers supporting variable bandwidths and it can relax the filtering requirements both in RF and analog baseband processing.The architecture described in Fig. 3.5.1 is based on a 4 th -order continuous-time ΔΣ modulator using 1-bit quantization. The ΔΣ coefficients have been optimized by placing the poles with a sufficient safety margin to the z-plane unit circle. This guarantees the stability of the modulator at the cost of less efficient quantization noise shaping. The optimization has been done in the discrete-time domain and then converted into the corresponding continuous-time coefficients. In addition, the careful excess loop-delay compensation improves robustness. Unlike normal baseband ΔΣ modulators, the first g m -C integrator stage is transformed into a bandpass filter stage with the switching arrangement between G m1 and capacitors C1-C4. The switches operate with a non-overlapping sequence loip, loqp, loim, loqm… with a period of 1/f LO i.e. four-phase LO signals with duty cycles slightly less than 25%. This structure maps a baseband lowpass filter onto an RF bandpass filter with equal absolute bandwidths centered around the LO frequency. Similarly, this structure combines the I and Q baseband ΔΣ modulator feedback branches into a single RF resonator. The second integrator stage of the ΔΣmodulator comprises an RF transconductance stage G m2 and a quadrature downconverting mixing stage with a four-phase 25% duty cycle switching sequence driving two differential Miller-integrator stages, one for I and one for Q. The following integrator stages are implemented as in a normal baseband continuoustime ΔΣ modulator.The three lowpass baseband filtering stages before the 1-b...

The effects of packaging on the performance of inductively degenerated common-emitter low-noise amplifiers (LNAs) are examined and the equations describing the input impedance, transconductance, voltage gain, and noise figure of the packaged amplifier are derived. From the equations, several guidelines for the LNA design are obtained and a systematic approach for the LNA design can be derived. Furthermore, by applying the formulas, the performance of the amplifier can be readily estimated and optimized in the very early stage of the circuit design, immediately as the process data is available. The measurement results of the implemented 0.35-m SiGe RF front-end with an inductively degenerated common-emitter LNA at 1.575 GHz agree well with calculations and simulations.

No abstract