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Presented for the first time is an accurate modelling hierarchy for mixed CNT bundle interconnects. Single-walled CNTs and multi-walled CNTs have been modelled as equivalent single conductor transmission lines and then combined to form a mixed CNT bundle interconnect, which is basically a multiple equivalent single conductor model. Two multiple equivalent single conductor interconnects have been taken to form the multiconductor transmission line model. The delays from transient analysis for both models for a unit bundle have been compared with the corresponding ones for SWCNT bundles and MWCNTs that exist in the literature. It is found that mixed CNT bundle interconnects are superior to both SWCNT bundle and MWCNT interconnects in terms of delay.Introduction: Carbon nanotubes (CNTs) are emerging as ideal materials for VLSI interconnect applications. The latest findings in this field emphasise mixed CNT bundles (MCB) as VLSI interconnects. CNTs are already popular for their outstanding electrical, mechanical and thermal properties. However, modelling and simulation of CNT interconnect structures is very important in attaining a fail-safe technology that is ready for immediate fabrication and prototyping. Transmission line parameters have been modelled for SWCNT bundles, MWCNTs and MCBs [1][2][3][4].This Letter considers the modelling aspects of mixed CNT bundles (MCB) as VLSI interconnects. The structure of MCB is more complex than that of SWCNTs and MWCNTs. So, direct analysis of these bundles is not possible. We are proposing a new hierarchical model by considering two CNTs, one SWCNT and one MWCNT, placed over the substrate. Then we have combined two MCB interconnects to form the multiconductor TL (MTL) model. First, the equivalent single conductor (ESC) model of inter-CNT capacitance is shown. A general perspective of MTL modelling of MCB interconnects is also discussed. Lastly, a transient analysis of the MESC as well as MTL models is performed to find the delay.

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Sub-threshold voltage operated circuits are the future for ultra-low-power applications. These circuits are inherently slow due to the very small sub-threshold currents. Here, the authors propose two approaches for improving the speed of SWCNT bundle interconnects driven by CNTFET-based circuits under sub-threshold conditions. First, the authors modulate the channel length of the CNTFETs that are used in the driver circuits to increase sub-threshold output current. The output current is maximum when the channel length is optimised to 15 nm. Second, the authors design driver circuits made of CNTFET-based inverters and transmission gates for SWCNT bundle interconnects at sub-threshold voltages. The authors consider five different configurations of the driver and load circuits. SPICE simulations show that transmission gates play a vital role in driver circuits by reducing the propagation delay and increasing the switching speed at high frequencies. Finally, the authors perform temperature-dependent analysis of the best cases from the proposed circuits and show that the propagation delay and power dissipated by them increases drastically at increased temperatures up to 500 K. 2 CNTFET current model CNTFET is regarded as the most advanced device which has similarities of MOSFET but has an advantage of working in