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In this paper, a flipping based reduced area high speed pipelined VLSI architecture for 2-D DWT is proposed. The direct implementation of lifting 9/7 filter has long critical path and requires large buffer size hence it is slower and requires large chip area. The proposed architecture has critical path of only one multiplier delay (T m ) with only 54 registers and buffer requirement will be only 2N to process N X N image. Critical path delay of T m is achieved with pipelining of flipping structure and buffer requirement of 2N is achieved with the overlapped strip based scanning and calculation of one intermediate coefficient. The proposed architecture is described using VHDL and implemented on FPGA.

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