Square Root Carry Select Adder (SQRT-CSLA) is accomplishing the noteworthy attention in the arena of VLSI (Very-Large-Scale Integration) systems as it can process the computations with high speed. Though the current trending SQRT-CSLA adder designing techniques are effective in various performance metrics, there is a possibility to improve the design addressing various performance metrics. This article proposes CSLA architecture by employing Zero Finding Logic using the Logic optimization technique (ZFCLOT). CSLA using ZFCLOT is designed, simulated, and synthesized using 90 nm cadence tools. CSLA using ZFCLOT achieves an area efficiency of 46.127% and a power efficiency of 48.4% as against to SQRT-CSLA.

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