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In this technical communication a voltage differencing transconductance amplifier (VDTA)-based unified grounded fractional/integer order negative/positive inductance emulator (IE) has been proposed which can be configured as (i) fractional order negative inductance emulator (FO-PIE) (ii) fractional order positive inductor emulator (FO-PIE) (iii) integer order negative inductance emulator (IO-NIE) and (iv) integer order positive inductor emulator (IO-PIE). The proposed unified IE is designed around a single VDTA and a grounded fractional capacitor (FC) or capacitor only. Non-ideal mathematical formulations of the proposed IE are carried out to enumerate the effect of non-idealities associated with VDTA. The functionality of proposed structure is validated through Virtuoso from Cadence tool suite using 180[Formula: see text]nm generic process design kit (gpdk) CMOS technology parameters. Power supplies of [Formula: see text][Formula: see text]V are used for VDTA simulation. The continued fraction expansion (CFE)-based rational approximation is used for FC implementation which is realized using RC ladder network truncated to 12th order. Fractional negative and positive inductances of value 78.13[Formula: see text][Formula: see text], 23.44[Formula: see text][Formula: see text] and 0.78[Formula: see text][Formula: see text] are realized and simulated. The topology is also tested for 1[Formula: see text]mH positive and negative integer order inductances. The simulation results corroborate with theoretical propositions. The applicability of the proposed structure is justified through two application examples namely parasitic fractional order inductance cancellation and fractional order high pass filter.