we propose an SRAM replica tracking circuit that reduces divergence of the replica path relative to normal read path (6-16% less Sense differential Requirement), thus improving the access time by 5-8%. The approach is compatible to power managed SRAMs having Retain till Access feature and also for non power managed SRAMs with no sense differential impact. Using This Replica tracing circuit Sense differential has been well tracked across all array and periphery voltages combinations which further improve the access time by 4-6%. Instances with this method 0.5-256Kb have been tested on a 28nm CMOS LP process. I.CONVENTIONAL TRACKING SCHEME Conventional SRAM replica tracking circuits impose penalty on read access/cycle time due to inclusion of dummy decoders and delay generators in the replica path for tracking wordline/bitline path delays across operating conditions [1]. With the prevalence of split rail architectures for SRAM for bitcell assist [2-3], tracking circuits need to work robustly across a combination of array/periphery voltages and process variations. Hence reducing divergence of tracking path compared to a normal read/write access path (that traverses both array and periphery voltage domains) is key to obtaining performance in split rail memories. In this work, an SRAM in low-power 28nm CMOS is built with 0.12ȝm2 bitcells [6] and uses a replica tracking circuit that provides lower divergence for the Wordline path across operating conditions. Figure 1 shows a conventional tracking circuit that uses dummy decoders and delay generators in the replica path. To support Adaptive Voltage Scaling (AVS) and split/dual rail architectures, the input array (VDDAR) and periphery (VDDPR) voltages can vary independently. The dummy decoders and delay generators can't be easily designed to match this voltage/process variation because the normal read access traverses array and periphery domains through the decoder (on VDDPR), Wordline driver + Level shifter (on VDDPR/VDDAR), bitcell (on VDDAR/VDDPR) etc.In case of Retain till Access (RTA) SRAMs [2,3], an extra component of RTA switch/diode circuit variation needs to be margined into the design robustness. In the absence of suitable matching between replica and normal access, additional timing margin addition is resorted to, thereby leading to a sub-optimal performance. Figure.1 Conventional SRAM replica tracking circuit II. PROPOSED TRACKING SCHEMEMultiple methods have been discussed in literature to counter the effects of variation on replica paths [4,5]. A commercially viable solution however needs a simple yet effective tracking method that reduces the variation impact on performance, yet does not require post fabrication calibration involving additional tester time for every chip. The key improvements of the proposed tracking method over prior art are:a.) the commonality of the normal access and replica path from the CLK to Wordline (CLK2WL) generation b.) the replica wordline generator circuit c.) the ability of the replica circuit to track variation across all per...

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