Electrical parameters such as threshold voltage (Vt), breakdown voltage (BVdss), source-drain current (Idss), and leakage (Igss) for surface p-channel MOSFETs are dependent upon channel doping. It was found that phosphorous out-gassing during anneal from doped ILDO could redope the channel and cause unexpected increases in both Vt and Vt variation. It is believed that the Vt variation results from two separate phosphorous out-gassing related mechanisms. One mechanism is the transport of phosphorous by the ambient gas through the furnace with a gradient from source to load. SCA results have shown that the phosphorous concentration was two orders of magnitude higher at the load end than at the source end, which was also confirmed by SIMS analysis. The other mechanism is diffusion oflocalized phosphorous from the TEOS, which does not difftise into the furnace ambient, but rather lingers between wafers. The corresponding Vt variation within a wafer, mostly caused by the latter localized effect,was measured to be 50 to 200 mV depending on poly implant dose. Lot to lot variations caused by both localized and furnace phosphorous have been found to be even larger.Two process modifications, undoped TEOS and a sandwich process, were made to eliminate the phosphorous out-gassing problem. While undoped TEOS does have the drawback of being unable to getter sodium, it was found that across waferuniformity and across flirnaceuniformity for both processes were substantially improved. Almost no phosphorous was detected by the SCA.

Abstract

This paper focuses on establishing a baseline for thin dielectric processes including: low temperature, dilute, stacked (TEOS), oxynitride, and high temperature annealed (grow‐anneal‐grow) oxidation. 105Å (total thickness) gate dielectrics were grown or deposited for this study. The stack oxide showed the highest Vbd yields for both large‐area and edge‐intensive capacitors, but the poorest Qbd. The N2O oxide yielded mediocre Vbd and Qbd. The low temperature and dilute oxides showed early breakdowns, but acceptable Qbd. 900°C thermal gate oxide showed slightly better average Vbd than low temperature and dilute oxides but comparable Qbd. The high temperature annealed oxide appears to have the best electrical performance, but the worst uniformity.

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