This work demonstrates a method of producing polycrystalline silicon TFTs using Flash Lamp Annealing (FLA) as a potential industrial counterpart to excimer laser annealing. Material uniformity and low-temperature dopant activation are explored within an investigation on solid-phase epitaxial regrowth for PMOS TFTs. Silicon self-implantation is used to partially amorphize select regions of FLA LTPS material, allowing epitaxial regrowth to incorporate boron into the resulting lattice. This regime is compared with total amorphization, in which epitaxial regrowth cannot occur. The effects of these different methods of recrystallization are demonstrated through transfer characteristics of fabricated transistors. Devices utilizing a partial pre-amorphization of FLA LTPS demonstrated effective hole channel mobilities of 40 - 50 cm2/(Vs) in low drain bias operation. Additionally, self-aligned TFTs using FLA are presented for the first time, with effective hole channel mobilities of 30 - 60 cm2/(Vs) in low drain bias operation using the same treatment.

Flash-lamp annealing (FLA) has been investigated for crystallization of patterned amorphous silicon (a-Si) in the fabrication of NMOS and PMOS Thin-Film Transistors (TFTs) on display glass. Samples were exposed with a xenon flash irradiance of ∼30 kW/cm2 and pulse duration of 200 μs, with bolometer measurements showing an integrated energy of ∼6 J/cm2. Non-self-aligned TFTs fabricated from the resulting polycrystalline silicon demonstrated electron and hole channel mobility values in excess of 300 cm2/(Vs) and 100 cm2/(Vs), respectively. According to the authors’ knowledge, this is the first report of CMOS TFTs demonstrated using the FLA technique.

This paper is an overview of the wafer and reticle positioning system of the Extreme Ultraviolet Lithography (EUVL) Engineering Test Stand (ETS). EWL represents one of the most promising technologies for supporting the integrated circuit (IC) industry's lithography needs for critical features below 100nm. EUVL research and development includes development of capabilities for demonstrating key EW technologies. The ETS is under development at the EW Virtual National Laboratory, to demonstrate EW full-field imaging and provide data that supports production-tool development. The stages and their associated metrology operate in a vacuum environment and must meet stringent outgassing specifications. A tight tolerance is placed on the stage tracking performance to minimize image distortion and provide high position repeatability. The wafer must track the reticle with less than &nm of position error and jitter must not exceed 10nm rms. To meet these performance requirements, magnetically levitated positioning stages utilizing a system of sophisticated control electronics will be used. System modeling and experimentation have contributed to the development of the positioning system and results indicate that desired ETS performance is achievable.

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