Self Ionized Plasma (SIP) Ti/TiN Process is used for barrier and glue layer before tungsten deposition in backend-of-the-line (BEOL). Long Throw technology and AC Bias are applied to gain better step coverage. But wafer backside arcing case happened frequently due to AC power side impact during SIP Ti/TiN deposition process. In this paper, the wafer backside arcing mechanism is studied and some effective improvement methods are proposed.

With the development of the products with more advanced technology nodes, new challenges continue to emerge in CMP processes. For example, there is a strong need to use lower down force in polishing process while maintaining a high removal rate to avoid low-k/ultra-low k dielectric film damage. The requirements for dishing, overpolish window, Cu residue clearance capability and surface defectivity, especially corrosion related defects become more stringent as copper lines become narrower and narrower. In this paper, we share our research efforts and results in developing a novel copper CMP slurry to overcome these performance challenges in Cu CMP process. In short, a well designed inhibitor system was applied in this slurry. The impacts of these inhibitors on the slurry performance including blanket removal rate/profile, static etch rate, dishing, Cu residue clearance capability and corrosion were evaluated through polishing experiments, electrochemistry evaluations, and laboratory tests simulating CMP aggressive conditions. With a synergetic effect of these inhibition systems, the slurry shows the excellent CMP performance

Chemical mechanical planarization (CMP) of copper is a critical step in advanced IC interconnects technology. The key performance metrics of a Cu CMP are the removal rate, removal rate profile, dishing and erosion, process window, and defectivity. Many researchers have studied the mechanisms of Cu CMP. The present investigations will mainly focus on the mechanical effects on advanced Cu CMP at low down forces. The two main mechanical factors, intrinsic properties of abrasives and polishing process conditions, were evaluated. It was found that the abrasive properties such as mean size, surface area, solid concentration and process conditions such as polishing down force and rotation speed have strong impacts on Cu CMP performance.

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As copper line width tightens to 100nm and below, except integration issues, reliability is another challenge. Barrier's performance is critical for the significant impact to interconnect speed and reliability. Ti based barrier is reported as an excellent barrier material from the standpoint of cost and performance, especially for the porous low-k ILD materials. While Ta based barrier is used mainly for its good adhesion, diffusion prevention. In this paper, we demonstrate a composite barrier with Ti adding to the Ta based bi-layer, which shown stable metal resistance while significantly improving reliability performance. Better interface is confirmed by TEM. Our study proved that such kind of Ti doped Ta barrier is better than the standard Ta N/Ta barrier.