This paper presents a low-voltage and powerefficient 10 bit successive-approximation register (SAR) analogto-digital converter (ADC). The input-range-adaptive (IRA) switching method is proposed to reduce the average switching power of capacitive digital-to-analog convertor (DAC) by 91% compared with the conventional approach. By utilizing the comparator as a voltage-to-time converter (VTC) with a timedomain quantizer, the implemented early-late (E/L) detection circuit, the input range is detected to eliminate the unnecessary DAC switching power efficiently. A prototype ADC chip is fabricated in 90 nm CMOS technology with an active area of 0.038 mm 2 . At 0.35-to-0.5 V supply voltage and 0.3-to-2 MS/s sampling rate with a Nyquist input, the ADC achieves a signalto-noise-plus-distortion ratio (SNDR) of 55.5 dB to 56.3 dB and a corresponding effective number of bits (ENOB) of 8.92 bit to 9.06 bit respectively with a power consumption of 0.3 µW to 2.5 µW and a resulting figure of merit (FoM) from 1.94 fJ/conversion-step to 2.32 fJ/conversion-step.Index Terms-Low power, low voltage, SAR ADC.

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