This work provides an efficient statistical electrothermal simulator for analyzing on-chip thermal reliability under process variations. Using the collocation-based statistical modeling technique, first, the statistical interpolation polynomial for on-chip temperature distribution can be obtained by performing deterministic electrothermal simulation very few times and by utilizing polynomial interpolation. After that, the proposed simulator not only provides the mean and standard deviation profiles of on-chip temperature distribution, but also innovates the concept of thermal yield profile to statistically characterize the on-chip temperature distribution more precisely, and builds an efficient technique for estimating this figure of merit. Moreover, a mixed-mesh strategy is presented to further enhance the efficiency of the developed statistical electrothermal simulator.Experimental results demonstrate that (1) the developed statistical electrothermal simulator can obtain accurate approximations with orders of magnitude speedup over the Monte Carlo method; (2) comparing with a well-known cumulative distribution function estimation method, APEX [Li et al. 2004], the developed statistical electrothermal simulator can achieve 215× speedup with better accuracy; (3) the developed mixedmesh strategy can achieve an order of magnitude faster over our baseline algorithm and still maintain an acceptable accuracy level.

In this work, we develop a statistical thermal simulator including the effect of spatial correlation under withindie process variations. This method utilizes the Karhunen-Loève (KL) expansion to model the physical parameters, and apply the Polynomial Chaoses (PCs) and the stochastic Galerkin method to tackle stochastic heat transfer equations. We demonstrate the accuracy and efficiency of our simulator by comparing with the Monte Carlo simulation, and point out that the stochastic thermal analysis is essential to provide a robust estimation of temperature distribution for the thermal-aware design flow .

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2D van der Waals (vdW) semiconductors hold great potentials for more‐than‐Moore field‐effect transistors (FETs), and the efficient utilization of their theoretical performance requires compatible high‐k dielectrics to guarantee the high gate coupling efficiency. The deposition of traditional high‐k dielectric oxide films on 2D materials usually generates interface concerns, thereby causing the carrier scattering and degeneration of device performance. Here, utilizing a space‐confined epitaxy growth approach, the authors successfully obtained air‐stable ultrathin indium phosphorus sulfide (In2P3S9) nanosheets, the thickness of which can be scaled down to monolayer limit (≈0.69 nm) due to its layered structure. 2D In2P3S9 exhibits excellent insulating properties, with a high dielectric constant (≈24) and large breakdown voltage (≈8.1 MV cm−1) at room temperature. Serving as gate insulator, ultrathin In2P3S9 nanosheet can be integrated into MoS2 FETs with high‐quality dielectric/semiconductor interface, thus providing a competitive electrical performance of device with subthreshold swings (SS) down to 88 mV dec−1 and a high ON/OFF ratio of 105. This study proves an important strategy to prepare 2D vdW high‐k dielectrics, and greatly facilitates the ongoing research of 2D materials for functional electronics.