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Recently, high speed communication packages require much larger chip sizes and the increased ball/lead counts (>3000), in order to meet high input/output (I/O) functionality, requires large size substrate (>50×50 mm2) to content it. Comparing with conventional substrate, thin core substrate brings about not only lower thickness of package, lightweight, but also short interconnection distance and good power integrity. For large size FCBGA with thin core, the challenge is how to effectively mitigate the assembly and reliability risks. Generally, it is not easy to control warpage using a stiffener ring or a lid for larger package size. Meanwhile, design for warpage control and TIM/chip interface stress reduction are conflicting in general. In addition, there has higher bump crack risk due to increased die center to bump distance resulted by larger die size. The solder resist opening of substrate and micro ball volume are considered to be the factors for solder bump stress reduction. The research work presented in this paper describes key factors for mitigating several assembly related issues, and the identification of the optimum structure design for successfully manufacturing larger size flip chip packages with thin core substrate.