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A b s t r a c tTraditionally, LR parsers are implemented as table interpreters. A parser generator creates tables whose entries are interpreted by the parser driver. Recent research shows that much faster LR parsers can be obtained by converting the table entries into directly executed code. This paper introduces new techniques for optimizing directly executable parsers. The optimization methods proposed here are based on the analysis of the characteristical properties of large programming language grammars. They include a new structure for the parsing algorithm, an adaptation of the classical chain rule optimization and a systematic approach to stack access minimization. A parser generator based on these techniques was developed. It generates directly executable LR parsers running up to seven times faster than comparable table interpreting parsers.

Instruction level parallelism (ILP) is a generally accepted means to speed up the execution of both scientific and non-scientific programs. Compilation techniques for ILP are in a sense "general-purpose" in that they do not depend on these source program characteristics. In this paper we investigate what can be gained by ILP techniques that are specialized for scientific code in the form of nested loop programs. This regular program form allows us to apply well-known techniques taken from the theory of loop transformation. We present a compilation algorithm based on both standard and non-standard transformations to increase fine-grained parallelism for software pipelining, to reduce communication overhead by integrated functional unit assignment and to minianize memory traffic by maximizing data reusability between adjacent computations. We present first results which show impressive speedups compared to conventionally software-pipelined code. Our investigations are based on the limited connectivity VLIW architectural model which is a realistic (= realizable) VLIW machine made up of multiple clusters with private register files.

Software pipelining is a well-known and effective technique for generating compact loop schedules for instruction level parallel computers. This paper presents the results of an experimental evaluation and comparison of different scheduling algorithms that generate software pipelines. We implemented these algorithms in an uniform retargetable compiler environment that can be instantiated by providing target machine descriptions. This environment and a carefully designed benchmark suite enable us to perform a fair comparison of the implemented techniques. We evaluate well-known non-hierarchical and hierarchical schedulers and a hybrid technique developed in our group. Our analysis indicates that scheduling algorithms based on variations of the "classical" non-hierarchical modulo scheduling technique will probably yield the most effective software pipelines.

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