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In this paper we report on spectrum use measurements carried out synchronously over the period of 48+ hours in seven European cities. Special care has been placed on harmonizing the measurement settings and equipment so as to obtain as comparable data as possible. We describe in detail the measurement setup, including the coordinated preparation activities carried out across the different measurement sites. We present preliminary analysis of the obtained data set, and particularly highlight similarities and differences in spectrum use between selected measurement locations. We plan to release later the full data set for research community for the further research.

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We demonstrate a reconfigurable engine for multipurpose spectrum sensing within the cost and power constraints of mobile devices. The analog part builds up on the Scaldio reconfigurable analog front-end [1]. The digital part is an innovative Digital Front-end for Sensing capable of performing a range of sensing algorithms [3], which has now been fully implemented as a chip. The goal of this demo is the first demonstration of the digital chip, integrated with an analog front-end, enabling real-time validation of the sensing engine. The setup is validated for DVB-T and LTE, two important candidates for future DySPAN networks, as well as for very fast spectrum sweeping. This is the first integrated low power solution that can achieve such a very fast spectrum sweeping, thanks to the integration of two innovative components.

The trend in wireless communication where terminals give their users ubiquitous access to a multitude of services drives the development of Software-Defined Radio (SDR) in deeply scaled CMOS. This is enhanced with the advent of LTE, a standard that is inherently so flexible that an SDR is its most economical implementation. This work presents an answer to that need with the development of a complete transceiver with RF, baseband and data converter circuits in 40nm LP CMOS.The full block diagram is shown in Fig. 25.5.1. As demonstrated in [1,2] direct up/down conversion is the most suitable architecture to build a competitive SDR radio. To permit FDD operation, the transceiver contains 2 independent double-VCO PLLs covering 6 to 12GHz. Thanks to the SDR concept, the analog baseband circuits and the PLL were re-used from the previous 45nm generation [1] and are just re-programmed to cope with the new 40nm device parameters.In the receiver, four parallel LNAs (1-2-3-5GHz) amplify the input signal with NF down to 1.5dB. They provide some selectivity against far out-of-band interference and reduce loss and cost of the multiband antenna interface. Each LNA (Fig. 25.5.2) uses shunt-shunt feedback to provide input matching, and a lowarea stacked inductor for gain shunt peaking, keeping the LNA area below 0.02mm 2 [3]. Load and feedback resistors are tunable to achieve a minimal gain step of 3dB. Current bleeding through IC lowers the voltage drop over the tunable load resistor. The voltage headroom for M0 is increased by IG, improving linearity and noise. Every LNA output is AC coupled and drives one of the 4 inputs of a multiplexing linear active balun.The downconversion to baseband is performed by a 25% duty-cycle passive mixer, built as an array of binary-scaled self-biased inverters Gmix that provide scalable transconductance gain. Gmix is AC coupled at input and output to limit leakage of second=order distortion components. The double-balanced NMOS switches are driven by a 25% duty-cycle LO and biased such that the mixer works only in the ON overlap region [4]. To compensate for mismatch between the quadrature switches, two 6b DACs Iip2 inject current at the nodes n1p and n1n. In combination with the DC offset compensation DACs IdcoI-IdcoQ, a mixer IIP2 better than 70dBm is achieved after calibration. A programmable 500kHz to 20MHz 5 th -order TILPF filters the signal before it is sampled and quantized by a fully dynamic 10b ADC. By using a passive charge-sharing architecture and redundancy as in [5], this SAR ADC consumes from 0.1mA to 4mA (I&Q channel) depending on the actual sampling frequency ranging from 1MS/s to 80MS/s. The transmitter consists of a TILPF, a passive mixer and a PPA (Fig. 25.5.3). All circuits have been designed for low out-of-band noise, to avoid an interstage SAW filter in FDD operation [6]. The TX chain starts with a 2 nd -order TILPF that has programmable bandwidth, programmable quality factor, the capability to trade linearity for power consumption and features 4 gain steps of 6dB.The upco...