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In this paper, we present a novel approach to schedulability analysis of Safety Critical Hard Real-Time Java programs. The approach is based on a translation of programs, written in the Safety Critical Java profile introduced in [21] for the Java Optimized Processor [18], to timed automata models verifiable by the Uppaal model checker [23]. Schedulability analysis is reduced to a simple reachability question, checking for deadlock freedom. Model-based schedulability analysis has been developed by Amnell et al. [2], but has so far only been applied to high level specifications, not actual implementations in a programming language. Experiments show that model-based schedulability analysis can result in a more accurate analysis than possible with traditional approaches, thus systems deemed non-schedulable by traditional approaches may in fact be schedulable, as detected by our analysis.Our approach has been implemented in a tool, named SARTS, successfully used to verify the schedulability of a real-time sorting machine consisting of two periodic and two sporadic tasks. SARTS has also been applied on a number of smaller examples to investigate properties of our approach.

We present a new open source model checker, opaal, for automatic verification of models using lattice automata. Lattice automata allow the users to incorporate abstractions of a model into the model itself. This provides an efficient verification procedure, while giving the user fine-grained control of the level of abstraction by using a method similar to CounterExample Guided Abstraction Refinement. The opaal engine supports a subset of the UPPAAL timed automata language extended with lattice features. We report on the status of the first public release of opaal, and demonstrate how opaal can be used for efficient verification on examples from domains such as database programs, lossy communication protocols and cache analysis.

Abstract-Home Automation systems provide a large number of devices to control diverse appliances. Taking advantage of this diversity to create efficient and intelligent environments requires well designed, validated, and implemented controllers. However, designing and deploying such controllers is a complex and error prone process. This paper presents a toolchain that transforms a design in the form of communicating state machines to an executable controller that interfaces to appliances through a service oriented middleware. Design and validation is supported by integrated model checking and simulation facilities. This is extendable to controller synthesis. This toolchain is implemented, and we provide different examples to show its usability.

Intelligence systems use many sensors and actuators, with a diversity of networks, protocols and technologies which makes it impossible to access the devices in a common manner. This paper presents the HomePort software, which provides an open source RESTful interface to heterogeneous sensor networks, allowing a simple unified access to virtually any kind of protocol using well known standards. HomePort includes means to provide event notification, as well as a tracing mechanism. The software is implemented and we report on initial experiments and provide an evaluation that shows the feasibility and scalability of the approach.