Past research aimed at increasing the sensitivity of capacitive pressure sensors has mostly focused on developing dielectric layers with surface/porous structures or higher dielectric constants. However, such strategies have only been effective in improving sensitivities at low pressure ranges (e.g., up to 3 kPa). To overcome this well‐known obstacle, herein, a flexible hybrid‐response pressure sensor (HRPS) composed of an electrically conductive porous nanocomposite (PNC) laminated with an ultrathin dielectric layer is devised. Using a nickel foam template, the PNC is fabricated with carbon nanotubes (CNTs)‐doped Ecoflex to be 86% porous and electrically conductive. The PNC exhibits hybrid piezoresistive and piezocapacitive responses, resulting in significantly enhanced sensitivities (i.e., more than 400%) over wide pressure ranges, from 3.13 kPa−1 within 0–1 kPa to 0.43 kPa−1 within 30–50 kPa. The effect of the hybrid responses is differentiated from the effect of porosity or high dielectric constants by comparing the HRPS with its purely piezocapacitive counterparts. Fundamental understanding of the HRPS and the prediction of optimal CNT doping are achieved through simplified analytical models. The HRPS is able to measure pressures from as subtle as the temporal arterial pulse to as large as footsteps.

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We investigate the 130nm (1.2V) and 280nm (2.5V) CMOS linear threshold voltage (Vtlin) and normalized saturation drain current (Idsat) versus channel width. Plots of Vtlin and Idsat versus channel width for different lengths are used to show the complex behavior as the channel width decreases. Both NMOS and PMOS Vtlin reach a maximum and then decrease as the width goes to W = 0.15um. NMOS Vtlin shows a 30% decease while PMOS Vtlin decreases 5% to 18%. We then show that the Vtlin behavior is caused by two opposite factors, Shallow Trench Isolation (STI) y-stress effect and Inverse Narrow Width (INW) effect. We eliminate x-stress as a factor by designing all the transistors with Sa = 10um. We observe that NMOS and PMOS Idsat decrease as the width decreases from 20um to 1um reaching a minimum, after that Idsat increases again. We believe this Idsat behavior is also caused by two opposite factors, STI y-stress effect and Delta Width, DW effect. The Idsat behavior is different for NMOS and PMOS. The STI y-stress effect is less pronounced for short channel NMOS transistors while the DW effect is weaker for short channel PMOS transistors.Index Terms-delta width, DW, inverse narrow width, INW, STI mechanical stress, x-stress, y-stress.

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