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Embedding advanced cognitive capabilities in batteryconstrained edge devices requires specialized hardware with new circuit architecture andin the medium/long term -new device technology. We evaluate the potential of recently investigated devices based on 2D materials for the realization of analog deep neural networks, by comparing the performance of neural networks based on the same circuit architecture using three different device technologies for transistors and analog memories. As a reference result, it is included in the comparison also an implementation on a standard 0.18 m CMOS technology. Our architecture of choice makes use of current-mode analog vector-matrix multipliers based on programmable current mirrors consisting of transistors and floating-gate non-volatile memories. We consider experimentally demonstrated transistors and memories based on a monolayer Molibdenum Disulfide channel and ideal devices based on heterostructures of multilayermonolayer PtSe2. Following a consistent methodology for device-circuit co-design and optimization, we estimate layout area, energy efficiency and throughput as a function of the equivalent number of bits (ENOB), which is strictly correlated to classification accuracy. System-level tradeoffs are apparent: for a small ENOB experimental MoS2 floating-gate devices are already very promising; in our comparison a larger ENOB (7 bits) is only achieved with CMOS, signaling the necessity to improve linearity and electrostatics of devices with 2D materials.