Trends of high power usage in portable consumer electronics and high speed designs is an important factor that biases the selection of an ASIC over a FPGA. ASICs are optimized to minimize the amount of logics used for a particular application; reductions in power are noticed when compared against FPGAs design for the same application. On the other hand, some FPGAs equipped with run-time reconfiguration, allow portions of the design to be changed on the fly. Having an appropriate methodology which creates a micro-level static architecture and reduces the reconfiguration overhead is used to lower the power consumption. This can allow the FPGA designs to be somewhat competitive against ASIC designs. This paper explores the reconfiguration methodology to lower the power consumption for the application of stereo rectification. The results obtained show significant savings in logical resources and power consumption when compared to ASIC-like FPGA implementations.

In this paper we present a concept of the selfassembling micro-architectures of Application Specific Virtual Processors for data-stream processing. The procedure for micro-architecture assembling is developed for Xilinx "Virtex" FPGA devices. It is shown that proposed approach allows a minimization of system resources for multi-task data-stream workload and gives ability for self-restoration of processing microarchitectures when hardware fault occurs. This Paper presents a description of system level architecture of runtime re-configurable multi-stream parallel processor for video applications and results gained on the prototype.

Despite of the success that programmable devices have enjoyed in the last two decades, architecture synthesis methodologies for Run-Time Reconfigurable (RTR) systems are still in their infancy. As the majority of consumer devices integrate multiple-functionality, the costeffectiveness becomes the main focus of computing systems design. This paper presents a novel architecture synthesis methodology for the cost-effective implementation of a multi-task and multi-mode workload. The proposed methodology creates a RTR system that changes its functionality in response to a dynamic environment and enables on-chip assembly of preconstructed components by synthesizing a workloadspecific static architecture. The proposed methodology presents novelties in design abstraction, partitioning method and in the procedure of deciding reconfiguration granularity. The experimental results show the cost benefits of the proposed architecture synthesis methodology saving 73% of area and 29.8% of power compared to fixed design approach for implementing multiple visual processors.

In today's consumer electronics the devices are crossing the boundaries by integrating the variety of functionalities to increase their market shares. As a result, the primary focus of designing consumer electronics lies upon implementation of costeffective, multi-task and multi-mode operations. We suggest a methodology for a cost-effective implementation of the reconfigurable system based on run-time reconfigurable FPGAs. The methodology focuses on extraction of the architecture that remains static throughout the lifetime of the application. The static architecture is constructed by analyzing the tasks associated with event(s) and distinguishing the level of task that needs to be in hardware. With the given architecture the system maintains inter-communication and only replaces the tasks that are necessary via reconfiguration. The idea of the proposed system is employed on the image processing of an autonomous satellite docking system because of tight physical limitations and high speed requirements. Obtained results prove that the run-time reconfigurable system architecture can provide a very efficient way to mosaic the micro-architecture that reuses limited hardware resources in time.

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