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This work reports on the triple‐level NAND flash cell realized from self‐amplified (SA) double gate (DG) tunneling‐based silicon‐oxide‐nitride‐oxide‐silicon (T‐SONOS) memory device. Through calibrated simulations, we show that capacitive coupling between the front gate and back gate can be used to store eight states (or 3 bits), that is, from “000” to “111,” in a T‐SONOS memory device with the readable difference between each level at lower programming voltages. The performance of the multilevel T‐SONOS cell is compared with the inversion mode SONOS (I‐SONOS) multilevel cell. Results highlight that gate length (Lg) scaling from 100 to 25 nm significantly deteriorates the threshold voltage associated with the lower states in the I‐SONOS multilevel cell. However, highly stable eight states can be achieved in a multi‐level T‐SONOS cell at Lg = 25 nm. The results highlight the potential of SA T‐SONOS cell for designing multilevel memory cell arrays.

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This paper presents a new optimized high-speed divide-by-8/9 dual modulus prescaler. Simulation results show 54% reduction in power consumption, 40% of speed improvement and almost 48% area reduction as compared to the conventional architecture. Power consumption in the proposed prescaler is reduced by eliminating one True-Single-Phase Clocked (TSPC) D Flip-Flop (DFF) from the standard divide-by-2/3 prescaler, replacing it with Pulse Extension Logic (PEL) circuit. Redundant stages from asynchronous divide-by-2 units were also removed to save more power and reduce more delay. The simulation results show that the prescaler is capable of running at 5.5[Formula: see text]GHz of maximum frequency with 1.9[Formula: see text]mW power consumption. The divider is implemented in 0.18[Formula: see text][Formula: see text]m CMOS technology with 1.8[Formula: see text]V power supply.

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