We present an innovative and comprehensive approach to model the resistance of local interconnect used in finFET technologies. Our parasitic resistance formulas for finFET source/drain regions cover both merged and unmerged fin processes. They have been verified with field solver simulation results, and are found to be accurate over a wide range of parameter values. Our local interconnect resistance model has been used in 14nm finFET technology, and is a critical part of compact models used in both extraction flow and schematic/pre-layout flow.

Through modeling, simulations, and experimental data, we show that FETs exhibit several width dependent characteristics purely due to un-correlated random variations among sub-threshold currents in different width segments. They include unit-width median sub-threshold current and constant-current threshold voltage. The width scaling relation for threshold voltage mismatch is different from Pelgrom scaling relation for sufficiently large variation when compared to the thermal voltage.

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