TFETs (tunnel field effect transistor) are providing solution to affairs associated with conventional MOSFET devices such as short-channel effects (SCEs) and limitation of minimum (60 mV/decade) subthreshold slope (SS). TFET is a p-i-n diode which conducts in reverse bias and behaves like a transistor due to tunnelling mechanism of the charge carriers across the barrier called band-to-band tunnelling (BTBT). TFETs face some critical problems like lower ON-state currents and ambipolar behaviour of conduction currents. The purpose of this review is to study a highly efficient TFET which provides significant improvements in ION/IOFF ratio with improved ON state current and ambipolar current suppression to enhance the performance of the device. TFET with multigate structure will be studied by using different dielectric and substrate materials. TFET may be considered as promising candidate over MOSFETs in low-power and high-speed switching circuits.

The characteristic and parametric dimensioning of Enclosed Layout (ELT) MOSFET with various geometric sizes and shapes has been taken into consideration for the study of irradiations and leakage at room temperature, which has been confirmed on several technological platforms. Using the most advanced technologies, parametric changes with minimum W/L ratios, layout area and input capacitance to reduce leakage current can improve the performance. The technique of hardening of the MOSFETs in contrary to total-dose radiation effects in space environment built in enclosure to the enclosed transistor for the elimination of edges, responsible of conventional NMOS transistors leakage path creation. High yielding, high level of integration, radiation immune, high speed, low costing and high volume production are the profit advantages of the enclosed layout.

This chapter represents some essential aspects of nanowires and their transport properties. Scaling of MOSFETs becomes a huge problem for industries due to short channel effects (SCEs) and sub-threshold leakage current. So, nanowires become a good solution to SCEs due to their structure. This chapter is divided into three parts. The first part gives a brief introduction of nanowire and different materials that can replace Si (channel material) and SiO2 (oxide material) due to their superior performance over Si. In the second part, the device structure and device structural measurement is discussed. In the third part, transport properties are discussed. This chapter shows the behavior of nanowire on changing different device materials and device dimensions. Electrical characteristics of Si and III-V based nanowires FETs will be analyzed and compared. High-k dielectric as oxide material also helps in improving device performance. HfO2 shows improvement in device characteristics over SiO2 taken as an oxide material. Junctionless nanowire MOSFET has also been designed and analyzed.