Low power is one of the arising trend in field of VLSI which can be used in multimedia bias employing colorful signal processing algorithms and armature. In utmost multimedia operation mortal beings can gather useful information from incorrect afFull Adderir. Thus we don’t need to produce an exact correct numerical afFull Adderir. So we're using different adders to apply this algorithm in signal processing. We design infrastructures for videotape and image contraction algorithms using the proposed approximate computation units and estimate them to demonstrate the efficiency of our approach. We also decide simple fine models for error and power consumption of these approximate adders. The approximate adders are reduced with complexity which are used in designing this algorithm. The proposed adders can achieve significant through afFull Adderir and total power reduction over conventional adders. Simulation results indicate up to 69% power savings using the proposed approximate adders, when compared to being executions using accurate adders.