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In this paper, a binary to residue number system architecture based on the 2 k _l modulo set. For the integer modulo operation (X mod m), (p, 2) compressors are used, where m is restricted to the values 2 k _l, for any value of k > 1 and X is a 16 bit number. The novel 3-2, 4-2 and 5-2 compressors are illustrated for efficient design, which are used as the basic building blocks for the proposed binary to residue converter designs. The 3-2, 4-2 and 5-2 compressors are used in place of half adder and full adder to reduce the delay, power consumption as well as the area of the circuit. The 4-2 and 5-2 compressors cell can operate reliably in any tree structured parallel multiplier at very low supply voltages. The proposed converter can be implemented by fast and simple architecture and also required less hardware.

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