Various technologies and algorithms are used for data transfer from one domain to another domain. First-In-First-Out (FIFO) method is the simplest among them but it requires multiple asynchronous clocks to access data. Advantage of favoring asynchronous is that the circuit can be reset with or without a clock present. The problem of multiple asynchronous clocks to access data in FIFO can be solved by the design of high throughput FIFO system which is briefly described in this paper. For achieving high throughput use of Globally Asynchronous Locally Synchronous (GALS) methodology is discussed in this paper.

An efficient high throughput FIFO (First-In-First-Out) system using GALS (Globally Asynchronous Locally Synchronous) technology is designed for data transfer from one domain to another domain with the development of a modeling and simulation framework whoseresults are obtained as RTL(Register-Transfer Level) Schematic. Integration of several of IP (Intellectual Property) cores into a single chip in order to fulfill the demand of latest applications, leads to various timing issues especially interfacing between the different clock domains. The GALS technology provides a clock distribution feature for the same. A general purpose 8-bit synchronous core designfavoringthe GALS technology is used for the designing. The model is implemented in VHDL (Very High Speed Integrated Circuits Hardware Description Language) with Xilinx ISE (Integrated Synthesis Environment) Design Suite 14.5 Version software and simulated using ISim tool. The synthesis results show improved throughput andreduced chip area usingGALS.