A parallel test Algorithm and design for built in self test (BIST) architecture to test the crosstalk faults in clustered arrays of TSVs (through silicon via) in 3DICs (Three dimensional Integrated Circuits) is discussed in this paper. Design of Modified Flexible Boundary scan cells to transfer the outputs to the functional cores or to the Output response analyzers (ORA) or signature analysers is proposed. Algorithm state machine (ASM) based design of BIST controller to generate the control and timing signals for launch and capture of test patterns is discussed. Parallel outputs capturing and signature generation mechanism is designed to reduce the time complexity.