Various video coding standards like H.264 and H.265 are used for video compression and decompression. These coding standards use multiple modules to perform video compression. Motion Estimation (ME) is one of the critical blocks in the video codec which requires extensive computation. Hence it is computationally complex, it critically consumes a massive amount of time to process the video data. Motion Estimation is the process which improves the compression efficiency of these coding standards by determining the minimum distortion between the current frame and the reference frame. For the past two decades, various Motion Estimation algorithms are implemented in hardware and research is still going on for realizing an optimized hardware solution for this critical module. Efficient implementation of ME in hardware is essential for high-resolution video applications such as HDTV to increase the decoding throughput and to achieve high compression ratio. A review and analysis of various hardware architectures of ME used for H.264 and H.265 coding standards is presented in this paper.

Motion estimation one of the advanced technique adapted in the industry for video coding and implemented in various applications. This work is focused on the efficient hardware implementation of the diamond search algorithm architecture. Among all the other Fast Search algorithms like three-step search, new three-step search, four-step search and diamond search (DS), the diamond search algorithm maintains the diamond shape search pattern and it gives faster search pattern and minimum absolute difference. When compared with the original diamond search (DS) algorithm, this modified diamond search algorithm requires less area and power maintaining the same performance. Other than the architectural level changes the low power synthesis is done and the results show that this design can be implemented effectively for an application that require fast search with low power requirements like IoT and sensor devices. The design has been implemented using Verilog HDL, synthesized using Synopsys DC compiler using 90nm technology.