No abstract

Purpose The purpose of this paper is to introduce a new linearization technique known as the passive linearizer technique which does not affect the power added efficiency (PAE) while maintaining a power gain of more than 20 dB for complementary metal oxide semiconductor (CMOS) power amplifier (PA). Design/methodology/approach The linearization mechanism is executed with an aid of a passive linearizer implemented at the gate of the main amplifier to minimize the effect of Cgs capacitance through the generation of opposite phase response at the main amplifier. The inductor-less output matching network presents an almost lossless output matching network which contributes to high gain, PAE and output power. The linearity performance is improved without the penalty of power consumption, power gain and stability. Findings With this topology, the PA delivers more than 20 dB gain for the Bluetooth Low Energy (BLE) Band from 2.4 GHz to 2.5 GHz with a supply headroom of 1.8 V. At the center frequency of 2.45 GHz, the PA exhibits a gain of 23.3 dB with corresponding peak PAE of 40.11% at a maximum output power of 14.3 dBm. At a maximum linear output power of 12.7 dBm, a PAE of 37.3% has been achieved with a peak third order intermodulation product of 28.04 dBm with a power consumption of 50.58 mW. This corresponds to ACLR of – 20 dBc, thus qualifying the PA to operate for BLE operation. Practical implications The proposed technique is able to boost up the efficiency and output power, as well as linearize the PA closer to 1 dB compression point. This reduces the trade-off between linear output power and PAE in CMOS PA design. Originality/value The proposed CMOS PA can be integrated comfortably to a BLE transmitter, allowing it to reduce the transceiver’s overall power consumption.

No abstract

No abstract

In this paper, an Integrated Phase Linearizer (IPL) technique is designed to improve the linearity performance of a CMOS power amplifier (PA). The IPL is integrated at the gate of the PA so that the effect of the parasitic gate-to-source ([Formula: see text]) capacitance of the main transistor is compensated by the linearizer. Thus, it improves the 3rd-order intermodulation point (OIP3) without trading-off the power added efficiency (PAE). The proposed solution is designed and fabricated in an 180[Formula: see text]nm CMOS technology process consuming the chip area of 2.25[Formula: see text]mm2. At the operating frequency of 2.45[Formula: see text]GHz, it exhibits a gain of 11.14[Formula: see text]dB with unconditional stability characteristics from 1[Formula: see text]GHz to 10[Formula: see text]GHz. Biased quiescent current of 19.35[Formula: see text]mA, the IPL-PA delivers a maximum output power of 15.20[Formula: see text]dBm with 40.86% peak PAE, 34.91[Formula: see text]dBm of peak OIP3 and maximum power consumption of 63.65[Formula: see text]mW at 2.45[Formula: see text]GHz with supply voltage headroom of 1.8[Formula: see text]V. The proposed linearization scheme proved to be an excellent solution for low-power transceivers integration.