-Several nanoscale computational fabrics based on various physical phenomena have been proposed in recent years. However, their integration with CMOS has only received limited attention. In this paper we explore some of these integration challenges focusing on registration and the overlay between layers. We propose and evaluate a new 3D integration approach by carefully mixing standard CMOS design rules and nanoscale constraints. We address the following questions: (i) How much overlay precision is necessary? (ii) What is the impact on yield if different overlays are used?, and (iii) How can we mitigate the overlay requirements? For a nanoprocessor design implemented in N 3 ASIC (a hybrid nanowire-CMOS fabric) we show that a 100% yield is achievable even for a today's known overlay of 3σ=±8nm (ITRS 2009). The N 3 ASIC fabric version retains 6X density advantage compared to a projected 16nm CMOS scaled design even after 3D integration.

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Emerging nano-device based architectures are expected to experience high defect rates associated with the manufacturing process. In this paper, we introduce a novel built-in heterogeneous fault-tolerance scheme, which incorporates redundant circuitry into the design to provide fault tolerance. A thorough analysis of the new scheme was carried out for various system level metrics. The implementation and analysis were carried out on WISP-0, a stream processor implemented on the Nanoscale Application Specific Integrated Circuits (NASIC) fabric. We show that intelligent assignment of redundancy levels and nanoscalevoting strategies across WISP-0 greatly improves area, effective yield and performance for the nano-processor. The new scheme outperforms homogeneous schemes for a defect range of 3% to 9.75% where the metric used is the product of performance and effective yield.

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