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Low dropout voltage regulators (LDO) use a large external capacitor, in the range of few micro-farads. These external capacitors occupy valuable board space, increase the IC pin count and prohibit System-On-Chip (SoC) solutions. The large external capacitor is replaced with a reasonable InF internal capacitor. The capacitor-less LDO is designed for an output voltage of 1.4V for a given supply voltage 2.2V using Cadence tool, UMCl80 PDK in 0.181.1m CMOS technology. The capacitor-less LDO responds within 80ns for a load current change of 0 -SmA consuming 300uA of ground current The Line and Load regulations achieved are 0.3mV and 0.22 mV respectively. The observed overshoot and undershoot voltages are less than SOm V in all process corners. The fast transient loop used has improved line regulation, load regulation and transient response.

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