Degradation behaviors of amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs) under negative bias stress (NBS) and negative bias illumination stress (NBIS) are investigated systematically. In some cases, a two-stage degradation behavior of a-IGZO TFTs is observed under both NBS and NBIS, which begins with a small positive shift of threshold voltage (V th), and is followed by a large negative V th shift. There is an intrinsic correlation between the degradations of NBS and NBIS. Quantitatively, both stress gate biases (V G) and temperature dependencies of V th of the two degradations are found to be the same and the recovery processes are also very similar. A unified model of NBS and NBIS is proposed to consistently explain the degradation behaviors of a-IGZO TFTs and their correlation. INDEX TERMS a-InGaZnO, thin-film transistors (TFTs), degradation, light illumination, gate bias stress.

Recently, rigid AMOLED display industry has stepped into mass production stage progressively. Meanwhile, flexible display has attracted more attention for its great potential to generate novel product market. However, when it comes to the mass production, flexible AMOLED display still faces quite a few technological challenges. In this paper, a 4.6-inch AMOLED display which can be rolled up under bending radius less than 3mm has been demonstrated, using process compatible to the current rigid AMOLED mass production line.

The lithium metal has been considered the most promising anode material for lithium ion batteries because of its high capacity and low electrochemical potential. However, the biggest problem lies in...

Instability of amorphous InGaZnO thin-film transistors under pulsed gate voltage (Vg) stress with steep transitions was experimentally investigated. The device threshold voltage (Vth) shifts positively depending on the number of pulse repetitions of the applied Vg pulses. For steeper pulse falling time (tf), more degradation occurs. In addition, for different base voltages of the Vg pulses, the maximum Vth degradation occurs under the condition that Vg pulses are symmetric about the flat band voltage. Such dynamic degradation is attributed to hot-carrier induced charge injection into the gate insulator and/or trapping at the interface near the source/drain regions during the tf transients.