Micro-Controller Units (MCUs) are widely adopted ubiquitous computing devices. Due to tight cost and energy constraints, MCUs often integrate very limited internal RAM memory on top of Flash storage, which exposes Flash to heavy write traffic and results in short system lifetime. Architecting emerging Phase Change Memory (PCM) is a promising approach for MCUs due to its fast read speed and long write endurance. However, PCM, especially multi-level cell (MLC) PCM, has long write latency and requires large write energy, which diminishes the benefits of its replacement of traditional Flash. By studying MLC PCM write operations, we observe that writing MLC PCM can take advantages of two write modes --- fast write leaves cells in volatile state, and slow write leaves cells in non-volatile state. In this paper, we propose a compiler directed dual-write (CDDW) scheme that selects the best write mode for each write operation to maximize the overall performance and energy efficiency. Our experimental results show that CDDW reduces dynamic energy by 32.4%(33.8%) and improves performance by 6.3%(35.9%) compared with an all fast(slow) write approach.

Abstract

Loops are typically the most computation intensive sections for embedded applications. Therefore, it is important to minimize the overall schedule length for loops during the compilation process. Register allocation and instruction scheduling are two key activities during a compilation process. These two activities exhibit a phase ordering problem: Instruction scheduling before register allocation could lengthen live ranges of variables which will create more conflicts and more costly spills; Register allocation before scheduling may result in the same register assignment to two independent variables which will limit the choices available for scheduling. This paper proposes a cooperative re-scheduling register allocation technique for loops that combines these two critical stages together to minimize the schedule length. The novelty of the proposed approach is that the responsibility for balancing the phase ordering problem lies within the register allocator, which can re-schedule the aggressive initial scheduling to minimize the schedule length. Experimental results show that the proposed approach can reduce overall schedule length by 12% on average compared to previous techniques.