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This paper presents the design of serial chip-to-chip communication at 20 Gbps including modeling and correlation for PCBs (Printed Circuit Boards) with FR4 substrate materials. The entire channel under investigation includes two packages, a 21-layer ceramic and a 12-layer organic, and a 22-layer PCB. A probing station, microprobes and a VNA are used to measure the entire channel S-parameters and the measurement is correlated to the simulation up to 20 GHz. Extended study for the channel with low loss PCB substrate material is simulated. Time-domain eye comparisons for the FR4 channel, low loss channel, and the FR4 channel with equalization are given. A general design rule as well as new technologies for the high-speed channel design at 20 Gbps and beyond are discussed and given in the conclusion.978-1-4244-6307-7/10/$26.00 ©2010 IEEE

Vias are widely modeled and investigated as they are one of the most concerns for the critical signal nets in high-speed digital systems. 3-D full-wave modelling can predict the electrical performance of a via accurately with correct model settings, which are related to the understood of the physics behind the signal transition and the wave propagation associated with the via. This paper will detail physics-based via model development by tracking the current path and mapping the via structures to circuit components/blocks where the peeling and partitioning method is used to decompose the entire via structure into via blocks. A simple via structure with the signal transitions from a microstrip to a microstrip is studied as an example. Good agreement has been achieved between the physics-based via simulation and the full-wave modeling in the frequency-domain with S-parameters and in the time-domain with eye-height and eye-width at different data rates.

SerDes (Serializer/DeSerializer) is widely used in gigabit Ethernet systems, fiber-optic communication systems, and storage applications for high-speed data transmission between different ASICs (application-specific integrated circuit) with the significant advantage of saving package pin numbers. The channel connecting the Serializer/DeSerializer in two different ASICs on a PCB (Printed Circuit Board) is the SerDes channel defined in the paper. Since DC biases in different ASICs are usually different for their Serializer/DeSerializer circuits, DC blocking capacitors are then necessary to block the DC path for signal transmission through the SerDes channel. It is known that the trace impedance on a PCB can be well controlled in manufacturing while it is difficult for a DC blocking via structure. Therefore, the blocking via structure is the main discontinuity contributor of the SerDes channel. In this paper, two different DC blocking via structures are studied. The performances of the two structures are compared and correlated up to 20 GHz with full-wave modelling and measurements. This study reveals the advantages/disadvantages of the two via blocking structures. A via optimization tool, which is based on the cavity resonance algorithm to speed up the optimization, is used to obtain the optimized parameters for the two blocking via structures, and the following full-wave simulations give further performance explorations of the two via structures.

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