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In this work, a new aluminum gate chemical mechanical planarization (CMP) model is proposed in high-k metal gate (HKMG) process for controlling and simulating the metal gate height variation. It systematically captures the effects of mechanical abrasion and concentrations of different types of chemical reagents on material removal rate and surface height evolution. Based on the fundamentals of steady-state oxidation reaction and etched removal in addition to mechanical abrasion, the combinational synergistic interaction is described by separate kinetic parameters such as process parameters, pad properties and slurry chemistry. It can be seen that the removal rate and the coupled effects of the chemical additives are determined from a closed-form equation, making use of the concepts of chemical mechanical equilibrium, chemical kinetics and contact mechanics. The model prediction results show good agreement with the collected experimental data. The metal gate dishing post-Al-CMP is found to increase with increasing the pattern density when the line space is fixed. The dishing value increases with increasing the pattern density up to a certain maximum and then it decreases for a fixed pitch. The present model can be adopted to analyze the influence of the design pattern structures, slurry properties, pad characteristics and polishing conditions on removal rate and wafer surface evolution. The governing equation of aluminum removal and dishing effect reveal some insights into the polishing process and can be used for assisting in HKMG test pattern design and performing the sensitivity analyzes of operating parameters on surface topography during Al-CMP.With the steady shrinkage of the feature size and device geometry of modern integrated circuits (ICs), chemical mechanical planarization (CMP) has emerged as one of the most important solution for surface local and global planarization. Aluminum metal CMP (Al-CMP) process was once a key solution to form the Al damascene interconnects in back-end-of-line (BEOL) application. 1,2 However, due to the low resistivity and better reliability performance of copper, the Cu damascene approach has eventually taken up the mainstream in BEOL interconnect structures.In recent years, the introduction of high-k metal gate (HKMG) structure has enabled the resumption of Moore's Law at the 45/32 nm nodes, when conventional Poly/SiON gate stacks run out of steam. HKMG technology which adopts a replacement metal gate (RMG) approach promises to enable conventional scaling of the transistor as well as reduced stand-by power. Intel had the first 45 nm HKMG processor in volume production in 2007 and most of the foundries introduce HKMG to fabricate their 32/22 nm devices and products. 3 Correspondingly, poly opening polish (POP) processing before dummy poly removed and Al-CMP implementation after work function metal deposited, have been developed to fabricate the HKMG products. 4,5 During the Al metal gate CMP process, the combinational effect of the polishing pad, abrasive particles and chemi...

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