Power electronic devices are essential components of high-capacity industrial converters. Accurate assessment of their power loss, including switching loss and conduction loss, is essential to improving electrothermal stability. To accurately calculate the conduction loss, a drain–source voltage clamp circuit is required to measure the on-state voltage. In this paper, the conventional drain–source voltage clamp circuit based on a transistor is comprehensively investigated by theoretical analysis, simulations, and experiments. It is demonstrated that the anti-parallel diodes and the gate-shunt capacitance of the conventional drain–source voltage clamp circuit have adverse impacts on the accuracy and security of the conduction loss measurement. Based on the above analysis, an improved drain–source voltage clamp circuit, derived from the conventional drain–source voltage clamp circuit, is proposed to solve the above problems. The operational advantages, physical structure, and design guidelines of the improved circuit are fully presented. In addition, to evaluate the influence of component parameters on circuit performance, this article comprehensively extracts three electrical quantities as judgment indicators. Based on the working mechanism of the improved circuit and the indicators mentioned above, general mathematical analysis and derivation are carried out to give guidelines for component selection. Finally, extensive experiments and detailed analyses are presented to validate the effectiveness of the proposed drain–source voltage clamp circuit. Compared with the conventional drain–source voltage clamp circuit, the improved drain–source voltage clamp circuit has higher measurement accuracy and working security when measuring conduction loss, and the proposed component selection method is verified to be reasonable and effective for better utilizing the clamp circuit.
Overcurrent failure caused by imbalanced current distribution is one of the universal failure forms of the SiC MOSFET module. The current sharing of parallel SiC MOSFETs is an important guarantee for the safe and reliable operation of parallel devices even the whole system. The existence of current coupling has a significant influence on the current sharing among paralleled SiC MOSFETs. Here, the mechanism of dynamic and static current imbalance under the different layouts resulting from current coupling generated by common branch impedance coupling and mutual inductance is comprehensively investigated by theoretical analysis and simulation validations. It is concluded that dynamic current imbalance is more serious when the drain confluence point and power source confluence point are on both sides than they are on the one side. While, the influence of the arrangement of two confluence points on the static current distribution is in reverse. Finally, a flexible and adjustable test bench is designed to verify the current sharing performance on the different layouts. The experimental results validate the correctness of the theoretical analysis. Based on these results, some guidelines are provided for the parallel‐connected application of SiC MOSFETs.
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