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FPGA (Field Programmable Gate Array) has the advantages of parallelism and reconfigurability, therefore, it is widely used in areas such as image processing, robotics and artificial intelligence. However, the development of FPGA currently involves too many hardware details, so it lacks extensibility for different platforms and flexibility for system level management and scheduling. In this paper, we propose an FPGA Virtualization Mechanism (FVM), which divides physical resources into pages (virtual resources). We use the technology of PR (Partial Reconfiguration) and the method of intermediate form to lift the extensibility and performance. We implement FVM in our platform VSC (Vary Super Computer System). Experiment results show that FVM can solve the problem of extensibility and flexibility, with high performance.

The explosive growth of video applications has produced great challenges for data storage and transmission. In this paper, we propose a new ROI (region of interest) encoding solution to accelerate the processing and reduce the bitrate based on the latest video compression standard H.265/HEVC (High-Efficiency Video Coding). The traditional ROI extraction mapping algorithm uses pixel-based Gaussian background modeling (GBM), which requires a large number of complex floating-point calculations. Instead, we propose a block-based GBM to set up the background, which is in accord with the block division of HEVC. Then, we use the SAD (sum of absolute difference) rule to separate the foreground block from the background block, and these blocks are mapped into the coding tree unit (CTU) of HEVC. Moreover, the quantization parameter (QP) is adjusted according to the distortion rate automatically. The experimental results show that the processing speed on FPGA has reached a real-time level of 22 FPS (frames per second) for full high-definition videos ([Formula: see text]), and the bitrate is reduced by 10% on average with stable video quality.