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The first single-event-upset (SEU) tests of the A T & T 6 4 K a n d 2 5 6 K S R A M s h a v e b e e n performed. Feedback resistor values for these parts ranged from 200kQ to IMQ. All were fabricated using the 1-pm 2-level poly, 2-level metal process. Ions used for these tests were Ar, Cu, Kr, and Xe providing a range of effective LET values from 20 to 129 MeV-cm2/mg. With t h e 64K S R A M operating at 4.5 volts and 90°C, an upset threshold LET of 30 MeV-cm2/mg and saturation crosssection of 1.5 x cm2 were measured with a nominal room temperature feedback resistance of 450kn. In Adam's 10% worst-case environment using the Petersen approximation, this implies an error rate of 1.3 x errors per bit-day. With a nominal 650kQ feedback resistance, a 256K SRAM had a calculated error rate of about 3 x 10-8 errors per bit-day at 4.5 volts and 90°C. This data agrees well with earlier data for a 1K-bit test chip. The minimal feedback resistance required to prevent upset vs. L E T is calculated by assuming an activation energy of 0.10 e V to estimate the decrease in feedback resistor value as a function of temperature.

This work presents recent results on Secondary Electron flash memory, and contrasts this approach to standard techniques for scaled, low power mass storage applications.

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