In this paper, an intuitive analysis of a phase noise reduction technique is done, and then a modified structure is proposed to achieve higher phase noise reduction than the original one. This method reduces the impact of noise sources on the phase noise by decreasing closed-loop gain in zero-crossings points and moving this high closed-loop gain to the non-zero-crossings points. This reduction tested on different scales and all of them showed improvement in the phase noise performance. In other words, this method reduces the phase noise by manipulating the operation region. Impulse sensitivity function (ISF) for the proposed structure shows degradation in comparison to the original structure. We have designed the proposed oscillator in 0.18 μm using CMOS TSMC standard technology. The proposed oscillator operates on 900 MHz, moreover, phase noise is-138.4 dBc/Hz at 1 MHz offset frequency while it consumes 3.11 mA from 1.8 V supply voltage.