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Floating point multiplication is of key importance to many modern applications. These applications usually involve floating point calculations with single and/or double precision format. For this reason, most modern processors have hardware support for single precision and double precision floating point multiplication. Achieving this goal however, usually affects the throughput since most FPUs convert the single precision operands to double precision and then translate again the result to single precision format. This output and precision is inadequate for many scientific computations like modeling of climatic conditions, processing of digital signals, graphic accelerators etc. All these higher level applications uses quadruple precision floating point arithmetic. The quadruple precision arithmetic specifications was included in the IEEE 754-2008 revised standard. Its precision is twice as compared to the double precision format. The design proposed in this paper performs all the three precision multiplication operation. The universal floating point multiplier is implemented using Vedic mathematics (Nikhilam Navatascaramam Dasatah Sutra).

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In the design of Integrated circuits, area plays a vital role because of increasing the necessity of portable systems. Carry Select Adder (CSLA) is a fast adder used in many dataprocessing processors for performing fast arithmetic functions. From the structure of the CSLA, the scope is reducing the area of CSLA based on the efficient gate-level modification. In this paper 4 bit, 8 bit, 16 bit, 32 bit, 64 bit and 128 bit Regular Linear CSLA, Modified Linear CSLA, Regular Square-root (SQRT) CSLA and Modified SQRT CSLA architectures have been developed and compared the area of these 4 types of CSLA and also applied these 4 bit, 8 bit, 16 bit, 32 bit, 64 bit and 128 bit CSLAs into 4X4 bit, 8X8 bit, 16X16 bit, 32X32 bit, 64X64 bit and 128X128 bit Vedic Multiplier (VM) respectively, then compared the area of Vedic Multiplier based on this adders. However, the Regular CSLA is still area consuming due to the dual Ripple Carry Adder (RCA) structure. For reducing the area of CSLA, it can be implemented by using a single RCA and an add-one circuit instead of using dual RCA. Comparing the Regular CSLA with Modified CSLA, the Modified CSLA has less area. The results and analysis show that the Modified SQRT CSLA provides better outcomes like less area and also the Vedic Multiplier using Modified Linear CSLA provides less area. This project was aimed for implementing high performance optimized FPGA architecture. Modelsim 10.0c is used for simulating the CSLAs and VM using CSLAs and synthesized using Xilinx PlanAhead13.4. Then the implementation is done in Virtex FPGA Kit.

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